A phase change memory, as typical of a memory provided with a programmable resistor device, is formed of a chalcogenide material, such as Ge, Sb or Te, which undergoes transition between an amorphous state and a crystalline state on joule heating, these states being used as two logic states for storage. If the phase change caused in the phase change memory by joule heating is to be from the low resistance state (set state) to the high resistance state (reset state), a high current is caused to flow for short time. For reverse transition, that is, for transition from the high resistance state (reset state) to the low resistance state (set state), it is necessary to cause a relatively low current to flow for longer time, usually for tens of ns to about 100 ns. For example Non-Patent Document 1 shows the configuration of a 64 Mb RAM employing a phase change memory in which the set time, that is the time needed for setting up the low resistance state, and the reset time, that is the time needed for setting up the high resistance state, are 120 ns and of the order of 50 ns, respectively.
The phase change memory may be read out within a time comparable to that of a DRAM. On the other hand, the time for transition from the high resistance state (reset state) to the low resistance state (set state) is longer, being from tens of ns to approximately 100 ns. For this reason, the phase change memory is intended to be used in many cases in combination with an asynchronous SRAM or a flash memory having a longer cycle time.
FIG. 6 depicts a timing chart for writing for the case of using a phase change memory in combination with a memory having an asynchronous SRAM interface. In FIG. 6, a word line is taken high responsive to address transition. A column selection line is activated simultaneously. When the column selection line is activated, data writing is commenced. The data writing comes to a close responsive to address transition of the next cycle. When the write cycle tWC is 70 ns, the write time can be performed until shortly after the start of the next cycle. Hence, tW=50 ns or thereabouts can be secured as an actual write time. In this manner, in case the write time of the phase change memory tWR=45 ns, it may be presumed to be possible to implement an SRAM-compatible non-volatile memory.
As a related technique, these is shown in Patent Document 1 a non-volatile semiconductor memory apparatus having memory cells capable of holding data as volatile data and non-volatile data. The memory cells capable of holding data as volatile data and non-volatile data may be the combination of, for example, cells of a DRAM, as volatile data memory means, and cells of an EEPROM, as non-volatile data memory means, or may also be cells having the functions of both volatile memory cells and non-volatile memory cells, through the use of a ferroelectric material. In this memory apparatus, when a start signal for starting a readout cycle for reading out data from a memory cell or a start signal for starting a write cycle for writing data in a memory cell is entered, a column address decision circuit verifies whether the row address (word line address) as entered for the directly previous readout/write cycle is the same as that entered for the current readout/write cycle. In case the row address of the directly previous readout/write cycle is different from that of the current readout/write cycle, volatile data is stored as non-volatile data in the memory cell as selected with the row address of the directly previous cycle, by way of a store operation. Subsequently, the non-volatile data, stored in the memory cell, as selected by the row address of the current cycle, is converted into volatile data, in order to read out the non-volatile data, by way of a recall operation. The so obtained volatile data is stored in the memory cell, in the sense amplifier connected to the relevant column address, and in, for example, a latch circuit other than the sense amplifier.
[Non-Patent Document 1]
Woo Yeong Cho et al., ‘A 0.18 μm 3.0 V 64 Mb Non-Volatile Phase-Transition Random-Access Memory (PRAM)’, 2004 IEEE International Solid-State Circuits Conference (ISSCC 2004/SESSION 2/NON-VOLATILE MEMORY/2.1, Feb. 16, 2004
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2001-210073A